The present subject matter relates to semiconductor memories, and more specifically, to three-dimensional vertical NAND flash memory.
Many types of semiconductor memory are known. Some memory is volatile and will lose its contents if power is removed. Some memory is non-volatile and will hold the information stored in the memory even after power has been removed. One type of non-volatile memory is flash memory which stores charge in a charge storage region of a memory cell. In a floating gate flash cell, a conductive floating gate, positioned between the control gate and the channel of a metal-oxide silicon field effect transistor (MOSFET or just FET), is used to store a charge. In a charge trap flash (CTF) cell, a layer of non-conductive material, such as a nitride film, is used to store charge between the control gate and the channel of a MOSFET. The voltage threshold of the MOSFET-based flash cell can be changed by changing the amount of charge stored in the charge storage region of the cell, and the voltage threshold can be used to indicate a value that is stored in the flash cell.
Some flash devices may store a single binary bit of data per cell. Such flash cells may be referred to as single-level cells (SLC). Other flash devices may allow for more than one binary bit of data to be stored in a single flash cell by using multi-level cells (MLC). In an MLC, the voltage threshold of the flash cell may be set to one of 2n different target levels to represent ‘n’ bits of storage. So for example, an MLC capable of storing 3 bits of information may have 8 different targeted voltage levels for its voltage threshold.
One architecture in common use for flash memories is a NAND flash architecture. In a NAND flash architecture, two or more flash cells are coupled together, source to drain, into a string, with the individual cell control gates coupled to control lines, such as word lines. Select gates, which may be standard FETs, may be coupled to the NAND string at either end, to couple the NAND string to a source line at one end of the NAND string, and to a bit line at the other end of the NAND string. Some NAND flash memories may use MLCs to increase storage density.
Some NAND flash strings may be fabricated vertically, with the memory cells of the NAND string stacked on top of each other. Vertically stacking the memory cells may provide a much higher density of memory per unit area. In some embodiments, the vertically stacked memory cells may share a common body and be coupled to a source line by a select gate source FET at the bottom of the string and be coupled to a bit line by a select gate drain FET at the top of the string.